There has been known a package substrate (a circuit substrate) on which a semiconductor chip such as an LSI chip is mounted. When a signal is transmitted at a transmission speed higher than, for example, 1 Gbps in a package substrate, the package substrate is generally adapted to have a strip line structure in which ground layers exist above and below the signal wiring. Further, in order to control the characteristic impedance of the wiring, there is a technology in which a wiring substrate is adapted to include a signal line made of a plurality of parallel conductors and including through hole conductors formed at both ends thereof, and include a power supply layer or a ground layer formed both above and below the signal line.
In the package substrate, the length of the signal wiring is at most about 3 cm (centimeter) long and the signal loss is not so much compared to a system board formed with a signal wiring having a wiring length of tens of centimeters. Therefore, an ability to cope with achieving high density or connection reliability has been important targets to be solved. However, when the signal is transmitted at the transmission speed higher than, for example, 10 Gbps, the signal loss in the package substrate is increased. Therefore, the signal loss in the package substrate is required to be reduced in order to achieve further improvement of the transmission speed.
Further, the development of technology has made it possible to manufacture a large scale semiconductor chip and the length of the signal wiring is increased due to the increase of the package substrate size accompanied by the manufacturing of the large scale semiconductor chip. Also, when the signal wiring length is increased, a signal loss is also increased. From this stand point of view, the reduction of the signal loss in the package substrate is also required. Accordingly, the technology described above may be applied to the package substrate in order to achieve the reduction of the signal loss in the package substrate. That is, the package substrate may be adapted to include a signal line made of a plurality of parallel conductors and including vias formed at both ends thereof, and include a power supply layer or a ground layer formed above and below the signal line.
However, it has been found out that when the signal line is made of a plurality of parallel conductors including vias formed at both ends thereof, a loss occurs due to the resonance depending on an interval between vias (a length of signal line) or a transmission speed (a frequency of transmission signal) and thus, the signal transmission may not be performed. That is, it has been found out that when the transmission speed is increased (either when the frequency of transmission signal becomes higher) or when the signal line length is increased as described above, a loss occurs due to the resonance and thus, the signal transmission may not be performed.
The following are reference documents.
[Document 1] Japanese Laid-Open Patent Publication No. 2006-351647,
[Document 2] Japanese Laid-Open Patent Publication No. 2011-100871, and
[Document 3] Japanese Laid-Open Patent Publication No. 2002-289737.